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MM74HCT373 * MM74HCT374 3-STATE Octal D-Type Latch * 3-STATE Octal D-Type Flip-Flop
February 1984 Revised February 1999
MM74HCT373 * MM74HCT374 3-STATE Octal D-Type Latch * 3-STATE Octal D-Type Flip-Flop
General Description
The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicongate CMOS technology, which provides the inherent benefits of low power consumption and wide power supply range, but are LS-TTL input and output characteristic & pin-out compatible. The 3-STATE outputs are capable of driving 15 LS-TTL loads. All inputs are protected from damage due to static discharge by internal diodes to VCC and ground. When the MM74HCT373 LATCH ENABLE input is HIGH, the Q outputs will follow the D inputs. When the LATCH ENABLE goes LOW, data at the D inputs will be retained at the outputs until LATCH ENABLE returns HIGH again. When a high logic level is applied to the OUTPUT CONTROL input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74HCT374 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions of the CLOCK (CK) input. When a high logic level is applied to the OUTPUT CONTROL (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs.
Features
s TTL input characteristic compatible s Typical propagation delay: 20 ns s Low input current: 1 A maximum s Low quiescent current: 80 A maximum s Compatible with bus-oriented systems s Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number MM74HCT373WM MM74HCT373SJ MM74HCT373MTC MM74HCT373N MM74HCT373WM MM74HCT373SJ MM74HCT373MTC MM74HCT373N Package Number M20B M20D MTC20 N20A M20B M20D MTC20 N20A Package Descriptions 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 1999 Fairchild Semiconductor Corporation
DS005367.prf
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MM74HCT373 * MM74HCT374
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View MM74HCT373
Top View MM74HCT374
Truth Tables
MM74HCT373 Output Control L L L H H H L X H L X X LE Data 373 Output H L Q0 Z Output Control L L L H L X H L X X MM74HCT374 Clock Data Output (374) H L Q0 Z
H = HIGH Level L = LOW Level Q0 = Level of output before steady-state input conditions were established. Z = High Impedance
H = HIGH Level L = LOW Level X = Don't Care = Transition from LOW-to-HIGH Z = High Impedance State Q0 = The level of the output before steady state input conditions were established.
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MM74HCT373 * MM74HCT374
Logic Diagrams
MM74HCT373
MM74HCT374
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MM74HCT373 * MM74HCT374
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC) DC Input Voltage (VIN ) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C 600 mW 500 mW -0.5 to +7.0V -1.5 to VCC +1.5V -0.5 to VCC +0.5V 20 mA 35 mA 70 mA -65C to +150C
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) 500 ns
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C.
Max 5.5 VCC +85
Units V V C
4.5 0 -40
DC Electrical Characteristics
VCC = 5V 10% (unless otherwise specified) Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT | = 20 A |IOUT | = 6.0 mA, VCC = 4.5V |IOUT | = 7.2 mA, VCC = 5.5V VOL Maximum LOW Level Voltage VIN = VIH or VIL |IOUT | = 20 A |IOUT | = 6.0 mA, VCC = 4.5V |IOUT | = 7.2 mA, VCC = 5.5V IIN IOZ Maximum Input Current Maximum 3-STATE Output Leakage Current ICC Maximum Quiescent Supply Current VIN = VCC or GND IOUT = 0 A VIN = 2.4V or 0.5V (Note 4)
Note 4: Measured per pin. All others tied to VCCor ground.
Conditions
TA = 25C Typ 2.0 0.8
TA = -40 to 85C 2.0 0.8
TA = -55 to 125C 2.0 0.8
Guaranteed Limits
Units V V
VCC 4.2 5.7 0 0.2 0.2
VCC- 0.1 3.98 4.98 0.1 0.26 0.26 0.1 0.5
VCC- 0.1 3.84 4.84 0.1 0.33 0.33 1.0 5.0
VCC- 0.1 3.7 4.7 0.1 0.4 0.4 1.0 10
V V V V V V A A
VIN = VCC or GND, VIH or VIL VOUT = VCC or GND Enable = V IH or VIL
8.0 1.0
80 1.3
160 1.5
A mA
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MM74HCT373 * MM74HCT374
AC Electrical Characteristics
MM74HCT373: VCC = 5.0V, tr = tf = 6 ns TA = 25C (unless otherwise specified) Symbol tPHL, tPLH tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tW tS tH Parameter Maximum Propagation Delay Data to Output Maximum Propagation Delay Latch Enable to Output Maximum Enable Propagation Delay Control to Output Maximum Disable Propagation Delay Control to Output Minimum Clock Pulse Width Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data CL = 45 pF RL = 1 k CL = 5 pF RL = 1 k 16 5 10 ns ns ns 18 25 ns 20 28 ns CL = 45 pF 21 30 ns CL = 45 pF Conditions Typ 18 Guaranteed Limit 25 Units ns
AC Electrical Characteristics
MM74HCT373: VCC = 5.0V 10%, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter Conditions CL = 50 pF CL = 150 pF CL = 50 pF CL = 150 pF CL = 50 pF CL = 150 pF RL = 1 k tPHZ, tPLZ Maximum Disable Propagation Delay Control to Output tTHL, tTLH Maximum Output Rise and Fall Time tW tS tH CIN COUT CPD Minimum Clock Pulse Width Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data Maximum Input Capacitance Maximum Output Capacitance Power Dissipation Capacitance (Note 5) OC = VCC OC = GND 16 5 10 10 20 5 52 20 6 13 10 20 24 8 20 10 20 ns ns ns pF pF pF pF CL = 50 pF RL = 1 k CL = 50 pF 8 12 15 18 ns 21 30 37 45 ns TA=25C Typ 22 30 25 32 21 30 30 40 35 45 30 40 TA=-40 to 85C TA=-55 to 125C Guaranteed Limits 37 50 44 56 37 50 45 60 53 68 45 60 Units ns ns ns ns ns ns
tPHL, tPLH Maximum Propagation Delay Data to Output tPHL, tPLH Maximum Propagation Delay Latch Enable to Output tPZH, tPZL Maximum Enable Propagation Delay Control to Output
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC.
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MM74HCT373 * MM74HCT374
AC Electrical Characteristics
MM74HCT374: VCC = 5.0V, tr = tf = 6 ns TA = 25C (unless otherwise specified) Symbol fMAX tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tW tS tH Parameter Maximum Clock Frequency Maximum Propagation Delay to Output Maximum Enable Propagation Delay Control to Output Maximum Disable Propagation Delay Control to Output Minimum Clock Pulse Width Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data CL = 45 pF RL = 1 k CL = 5 pF RL = 1 k 20 5 16 ns ns ns 17 25 ns 19 28 ns CL = 45 pF Conditions Typ 50 20 Guaranteed Limit 30 32 Units MHz ns
AC Electrical Characteristics
MM74HCT374: VCC = 5.0V 10%, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Clock Frequency CL = 50 pF CL = 150 pF CL = 50 pF CL = 150 pF RL = 1 k tPHZ, tPLZ Maximum Disable Propagation Delay Control to Output tTHL, tTLH Maximum Output Rise and Fall Time tW tS tH CIN COUT CPD Minimum Clock Pulse Width Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data Maximum Input Capacitance Maximum Output Capacitance Power Dissipation Capacitance (Note 6) OC = VCC OC = GND 16 20 5 10 20 5 58 20 25 5 10 20 24 30 5 10 20 ns ns ns pF pF pF pF CL = 50 pF RL = 1 k CL = 50 pF 8 12 15 18 ns 21 30 37 45 ns 22 30 21 30 to Output tPZH, tPZL Maximum Enable Propagation Delay Control to Output Conditions TA = 25C Typ 30 36 46 30 40 tPHL, tPLH Maximum Propagation Delay TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 24 45 57 37 50 20 48 69 45 60 MHz ns ns ns ns Units
Note 6: CPD determines the no load power consumption, PD = CPD V CC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + I CC.
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MM74HCT373 * MM74HCT374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com
MM74HCT373 * MM74HCT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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MM74HCT373 * MM74HCT374 3-STATE Octal D-Type Latch * 3-STATE Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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